Techniques and circuits for time-interleaved injection locked Voltage Controlled Oscillators with jitter accumulation reset

ABSTRACT

Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

TECHNICAL FIELD

The proposed solution relates to jitter accumulation prevention involtage controlled oscillators, and in particular to systems, circuitsand techniques for time-interleaved injection locked voltage controlledoscillators with jitter accumulation reset.

BACKGROUND

For example, in digital communications, it is known that the phase noiseof a Voltage Controlled Oscillator (VCO) is greater at low frequencieswith respect to a carrier frequency due to an increase of flicker noisepower magnitude at low frequencies. Injection locking allows phasetracking of a reference clock. It is for this reason that VCOs aregenerally employed locked to a clean reference clock source to filterout low-frequency intrinsic phase noise of the VCO. Due to positivefeedback that enables VCOs to oscillate, the noise created by everyelement in a VCO within a phase locked loop gets amplified over time.This positive feedback noise enhancement is referred to as jitteraccumulation and is schematically illustrated in FIG. 1. For the purposeof concise description herein, jitter accumulation can be summarized asa timing uncertainty in VCO output signal transitions, transition timinguncertainty which grows over time.

In particular, injection locked VCOs exhibit jitter accumulationdependent on the effective bandwidth achieved by the injection lockingprocess. Employing a higher reference clock frequency would result in ahigher effective bandwidth and better jitter performance. However, amain shortcoming of employing traditional injection locking is the factthat jitter accumulation is directly proportional to the reference clockfrequency.

There is a need to reduce jitter accumulation in VCOs for a variety ofapplications.

SUMMARY

Identical VCOs having the same output frequency and phase are employedto mitigate jitter accumulation. Embodiments of the proposed solutioninclude techniques and circuits employing a pair of time-interleavedinjection locked VCOs such that when one VCO is oscillating the otherVCO is turned off and vice versa.

In other embodiments, employing a plurality of cascaded injection lockedVCOs is proposed.

In yet other embodiments, deselected VCO(s) can be reset to “flush” theaccumulated jitter when not in use.

In accordance with an aspect of the proposed solution there is provideda VCO circuit, the circuit comprising: a plurality of VCO branchcircuits, each VCO branch circuit employing a reference clock signal toprovide a VCO output signal; a multiplexer configured to output one ofthe plurality of VCO output signals; and a control circuit configured tooutput the VCO output signal of each VCO branch circuit via round robinselection at the multiplexer and configured to turn off a remaining VCOin at least one deselected VCO branch circuit, wherein accumulatedjitter increases over time in each VCO branch circuit and operation ofthe control circuit limits jitter accumulation below an acceptablethreshold σ_(ΔT) via the round robin selection and turn off repeatedlywith a period ΔT.

In accordance with another aspect of the proposed solution there isprovided a transceiver comprising: a pulse generator providing referenceclock signal including a train of pulses at common reference clockfrequency; a plurality of VCO branch circuits, each VCO branch circuitemploying the reference clock signal to provide a VCO output signal; amultiplexer configured to output one of the plurality of VCO outputsignals; and a control circuit configured to output the VCO outputsignal of each VCO branch circuit via round robin selection at themultiplexer and configured to turn off a remaining VCO in at least onedeselected VCO branch circuit, wherein accumulated jitter increases overtime in each VCO branch circuit and operation of the control circuitlimits jitter accumulation below an acceptable threshold σ_(ΔT) via theround robin selection and turn off repeatedly with a period ΔT.

In accordance with another aspect of the proposed solution there isprovided a method of operating VCO circuit, the method comprising:injecting a reference clock signal into a plurality of VCO branchcircuits, each VCO branch circuit employing the reference clock signalto provide a VCO output signal; and selecting the VCO output signal ofeach VCO branch circuit round robin fashion via a multiplexer andturning off remaining VCOs in deselected VCO branch circuits, themultiplexer being configured to output one of the plurality of VCOoutput signals, wherein accumulated jitter increases over time in eachVCO branch circuit and jitter accumulation is limited below anacceptable threshold σ_(ΔT) via the round robin selection and turn offrepeatedly with a period ΔT.

BRIEF DESCRIPTION OF THE DRAWINGS

The proposed solution will be better understood by way of the followingdetailed description of embodiments of the invention with reference tothe appended drawings, in which:

FIG. 1 is schematic plot showing jitter accumulation in an output of aVoltage Controlled Oscillator (VCO);

FIG. 2 is a diagram illustrating a circuit schematic in accordance withan embodiment of the proposed solution;

FIG. 3 is a schematic plot representative of a signal diagram of thecircuit illustrated in FIG. 2 in accordance with the first embodiment ofthe proposed solution;

FIG. 4 is a schematic plot showing measured accumulated jitter of atypical injection locked VCO ring oscillator of FIG. 1 compared tomeasured accumulated jitter of a pair of injection locked VCOs operatingin time-interleaved fashion in accordance with the first embodiment ofthe invention illustrated in FIGS. 2 and 3;

FIG. 5 is a schematic plot showing measured accumulated jitter ofanother typical injection locked VCO ring oscillator of FIG. 1 comparedto measured accumulated jitter of another pair of injection locked VCOsoperating in time-interleaved fashion in accordance with the firstembodiment of the invention illustrated in FIGS. 2 and 3;

FIG. 6 is a diagram illustrating another circuit schematic in accordancewith another embodiment of the proposed solution; and

FIG. 7 is a schematic plot representative of a signal diagram of thecircuit illustrated in FIG. 6 in accordance with the second embodimentof the proposed solution;

wherein similar features bear similar labels throughout the drawings.While the sequence described can be of significance, reference to“first”, “next”, “subsequent”, “last”, “left to right”, “top” and“bottom” qualifiers in the present specification is made solely withreference to the orientation of the drawings as presented in theapplication and does not imply any absolute spatial orientation.

DETAILED DESCRIPTION

It is understood that the jitter accumulation illustrated in FIG. 1 isgreatly exaggerated in time solely for purposes of simplifyingdescription herein. Specifically, an injection locked VCO operates withdesired jitter characteristics after turn-on following a briefstabilization period (not shown). Accumulated clock jitter surpasses anacceptable threshold σ_(ΔT) after a period of operation ΔT. Whileindividual VCO devices poses output frequency, phase and jittervariances, VCOs manufactured in the same batch express similarcharacteristics. Identical VCOs manufactured on the same wafer expressvery similar frequency and phase characteristics.

In the following, references to a “subsequent” cycle/transition areunderstood to refer to a cycle/transition following later in time butnot necessarily an immediately sequential cycle/transition. The numberof intervening cycles/transitions can be selected by appropriate delaycircuits not shown solely for concise description herein. Such delaycircuits include frequency dividers, counters, RC delay circuits,cascaded inverters, etc. to implement the “interleaved” and/or“cascaded” operation presented hereinbelow.

In order to reduce or to mitigate jitter accumulation over time,techniques and circuits employing a combination of multiple identicalinjection locked VCOs having the same output frequency and phase areproposed. Since injection locking allows phase tracking of the referenceclock; identical VCOs using the same reference clock will have the sameoutput frequency and phase.

In accordance with an embodiment of the proposed solution, the output ofa time-interleaved pair of identical injection locked VCOs is employedin a circuit 100 schematically represented in FIG. 2. The principle ofoperation of circuit 100 can be summarized as turning off an unselectedVCO when the other selected VCO is oscillating and vice versa. This hasthe effect of providing the least jitter affected output of each VCO foruse.

A very stable reference clock 102 operating at a lower sub-harmonic ofthe VCOs 114 is employed to provide timing in circuit 100. A pulsegenerator 104 converts the reference clock 102 signal into a train ofshort pulses 106 at the same frequency as that of the reference clock102. Pulses 106 are employed to activate a driver 108 in each VCO branch110 of the overall circuit 100. The output of each driver 108 injectssub-harmonic pulses into an injection locked system 112 for exampleincluding a ring VCO 114 made of inverters 116 as injection lockedsystem112 operates at higher frequency. Injection locking allows phasetracking of reference clock 102. Identical VCOs 114 in differentbranches 110 of circuit 100 will output a common frequency and phase 118via multiplexer 120 at the VCO operating frequency.

Control signals can be used to disrupt one or the other of the injectionlocked system 112 in each VCO branch 110 via a corresponding switch 122.The control signals are also used to select the output of the VCO branchcircuit 110 currently oscillating for output from the multiplexer 120.FIG. 3 is a schematic plot representative of a timing diagram of thecircuit illustrated in FIG. 2 in accordance with the first embodiment ofthe proposed solution. The top signal trace illustrates the signaloutput by injection locked system 112 of VCO1 provided to themultiplexer 120, the middle signal trace illustrates the signal outputby the injection locked system 112 of VCO2 provided to the multiplexer120 and the bottom signal trace illustrates the output 118 out ofmultiplexer 120.

As time progresses from left to right, the injection locked system 112using VCO1 has recently been turned on (to the left off page), has lowaccumulated jitter and is selected as the multiplexer output 118. At thesame time, the injection locked system 112 for VCO2 is turned off(disrupted by turning off switch 122), VCO2 is in a relaxation state,and the injection locked system 112 for VCO2 does not output a usefulsignal to multiplexer 120. This mode of operation continues for a numberof cycles, both at the reference clock frequency and/or at the VCOfrequency, for the time period ΔT from the Start VCO1 during which theVCO1 output is known to have an accumulated jitter under the acceptablethreshold σ_(ΔT). Cycle counting circuitry would be understood by aperson of skill in the art and is omitted from illustration in FIG. 2solely to simplify description herein. Accumulated jitter is expected toincrease close to acceptable threshold σ_(ΔT) before expiration of ΔTfrom when Start VCO1 was asserted as illustrated in FIG. 1.

Before this first ΔT expires, VCO2 is started and the phase injectionlocked system 112 using VCO2 oscillates for a few cycles at the VCOfrequency which allows VCO2 to stabilize. Starting VCO2 also begins asecond ΔT period during which VCO2 is regarded to have accumulatedjitter below the σ_(ΔT) acceptable threshold. After VCO2 is stabilized,the control circuit(s) switch the multiplexer 120 to select the outputof VCO2 as the multiplexer output 118. After a few VCO output cycles atthe VCO frequency, or after about one reference clock cycle, VCO1 isstopped by disrupting (122) the injection locked system 112 using VCO1.VCO1 is allowed to relax during most of the second ΔT period withoutproviding a useful output. This mode of operation continues for a numberof cycles, both at the reference clock frequency and at the VCOfrequency, for the time period ΔT from the Start VCO2 during which theVCO2 output is known to have an accumulated jitter under the acceptablethreshold σ_(ΔT).

VCO1 is started again close to the end of second ΔT period while VCO2 isstill regarded to have accumulated jitter below the σ_(ΔT) acceptablethreshold. After VCO1 stabilizes, the control circuit(s) switch themultiplexer 120 to select the output of VCO1 to provide output 118.After a few VCO output cycles at the VCO frequency, or after about onereference clock cycle, VCO2 is stopped by disrupting (122) the injectionlocked system 112 using VCO2. The timing diagram repeats endlessly fromthe left to the right.

Thus, when one VCO 114 is oscillating the other VCO 114 is suppressedand vice versa using alternating injection locked VCOs to mitigatejitter accumulation. Each suppressed VCO 114 enters its relaxationperiod. Being injection locked, a pair of identical VCOs has acontinuous phase output, this results in a continuous output signal 118with reduced jitter accumulation. The bottom signal trace in FIG. 3illustrates clipped jitter accumulation from each VCO branch circuit 110as output by the multiplexer 120. Accumulated jitter increases from alow value at the beginning of each ΔT period to a maximum value belowacceptable threshold σ_(ΔT) towards the end of each ΔT. In accordancewith the proposed solution, by toggling between VCOs 114 the accumulatedjitter at the output of the multiplexer 120 is limited to a maximumaccumulated jitter value below acceptable threshold σ_(ΔT) and does notgrow unbounded.

It is understood that FIGS. 2 and 3 are highly schematic. While drivers108 can be very fast, in practice glitches can be reduced by employingmatched drivers 108 to inject the reference clock signal pulses 106 intoeach VCO circuit branch 110 for oscillation. Such matched drivers 108can be selected from the same manufacturing run, preferably identicaldrivers 108 are wafer level manufactured on the same wafer.

Prototypes have been implemented according to the techniques and methodsillustrated in FIGS. 2 and 3 and have been experimentally measured. Theprototypes show improved performance compared to typical VCO injectionlocking.

In a first test, a sub-harmonic reference clock 32 times slower than theVCO oscillation frequency was used as the injected signal 106 to atypical VCO ring oscillator (FIG. 1). The measured phase noise isillustrated by the dashed line in FIG. 4. Then, the same injectionsignal 106 was applied to time-interleaved VCOs as described hereinabovewith reference to FIGS. 2 and 3. The in-band phase noise at 1 MHz offsetfrom the carrier improved by about ˜4 dB as illustrated by the solidline compared to the dashed line in FIG. 4.

The same experiment was performed again with a sub-harmonic referenceclock 64 times slower than the VCO oscillation frequency and a similarperformance improvement was observed as illustrated in FIG. 5. Thein-band phase noise at 1 MHz offset from the carrier improved by about˜7 dB as illustrated by the solid line compared to the dashed line.

Additionally, it has been observed that inverters 116 and VCO 114 incorresponding injection locked system 112 include parasitic capacitances(not shown) which have been found to affect jitter and ultimately havean effect on the accumulated jitter. In accordance with anotherembodiment of the proposed solution, reset means are employed to reduceparasitic capacitances in each injection locked system 112.

FIG. 6 illustrates a circuit schematic 200 in accordance with the secondembodiment of the proposed solution showing time-interleaved identicalinjection locked VCOs using a reset pulse to “flush” the accumulatedjitter. Features in common with circuit schematic 100 retain samelabels. Circuit 200 employs switches 222 to inject a reset pulse afterthe corresponding VCO 114 is turned off to relax. The timing andapproximate duration of each reset pulse RST is illustrated in FIG. 7for each VCO branch 110. It is understood that injection locked system112 takes some time to stabilize after the reset pulse. Employing thejitter reset pulse RST results in reducing accumulated jitter andtherefore in better performance.

While reduced jitter accumulation has been described employing a pair ofidentical injection locked VCOs in an interleaved fashion, furtherjitter accumulation reductions can be provided by employing three ormore identical injection locked VCOs selected in a cascading fashion.

Benefits can be derived from implementing the proposed solution atwafer-level component manufacture and/or chip-level componentproduction, for example in phase locked loops (PLLs), VCOs, Digital toAnalog Converters (DACs), digital clock trees, etc. otherwise havingunacceptable jitter to improve the operation of devices and systemsincluding transceivers, modems, line cards, etc. incorporating suchcomponents. Additional benefits can be derived from low power componentoperation and compact component/device design.

While the invention has been illustrated and described with reference topreferred embodiments thereof, it will be recognized by those skilled inthe art that various changes in form and detail may be made thereinwithout departing from the spirit and scope of the invention as definedby the appended claims.

What is claimed is:
 1. A Voltage Controlled Oscillator (VCO) circuit,the circuit comprising: a plurality of VCO branch circuits, each VCObranch circuit employing a reference clock signal to provide a VCOoutput signal; a multiplexer configured to output one of the pluralityof VCO output signals; and a control circuit configured to, via a roundrobin selection of a period ΔT, output the VCO output signal of each VCObranch circuit at the multiplexer and turn off a VCO in at least onedeselected VCO branch circuit, wherein accumulated jitter increases overtime in each VCO branch circuit and operation of the control circuitlimits jitter accumulation below an acceptable threshold σ_(ΔT) via theround robin selection and turn off.
 2. A circuit as claimed in claim 1,wherein the plurality of VCO branch circuits comprise identical VCOcomponents manufactured on the same wafer.
 3. A circuit as claimed inclaim 1, wherein each VCO branch circuit comprises an injection lockedsystem including a corresponding driver configured to inject thereference clock signal into the corresponding injection locked system,wherein identical driver components are manufactured on the same wafer.4. A circuit as claimed in claim 3, wherein each injection locked systemcomprises a ring oscillator including a switch and a plurality ofinverters, and the control circuit is configured to actuate the switchto turn off the corresponding VCO in a deselected VCO branch.
 5. Acircuit as claimed in claim 1 comprising a pair of VCO branch circuitswherein round robin selection interleaves the outputs of the pair of VCObranch circuits.
 6. A circuit as claimed in claim 1 comprising at leastthree VCO branch circuits wherein round robin selection cascades theoutputs of the at least three VCO branch circuits.
 7. A circuit asclaimed in claim 3, wherein each VCO branch circuit further comprises areset switch configured to inject a reset signal into the correspondinginjection locked system after oscillation in the corresponding VCObranch circuit is turned off, to flush accumulated jitter in theinjection locked system.
 8. A transceiver comprising: a pulse generatorproviding a reference clock signal including a train of pulses at acommon reference clock frequency; a plurality of Voltage ControlledOscillator (VCO) branch circuits, each VCO branch circuit employing thereference clock signal to provide a VCO output signal; a multiplexerconfigured to output one of the plurality of VCO output signals; and acontrol circuit configured to, via round robin selection of a period ΔT,output the VCO output signal of each VCO branch circuit at themultiplexer and turn off a VCO in at least one deselected VCO branchcircuit, wherein accumulated jitter increases over time in each VCObranch circuit and operation of the control circuit limits jitteraccumulation below an acceptable threshold σ_(ΔT) via the round robinselection and turn off.
 9. A transceiver as claimed in claim 8, whereinthe plurality of VCO branch circuits comprise identical VCO componentsmanufactured on the same wafer.
 10. A transceiver as claimed in claim 8,wherein each VCO branch circuit comprises an injection locked systemincluding a corresponding driver configured to inject the referenceclock signal into the corresponding injection locked system, whereinidentical driver components are manufactured on the same wafer.
 11. Atransceiver as claimed in claim 10, wherein each injection locked systemcomprises a ring oscillator including a switch and a plurality ofinverters, and the control circuit is configured to actuate the switchto turn off the corresponding VCO in a deselected VCO branch.
 12. Atransceiver as claimed in claim 8 comprising a pair of VCO branchcircuits wherein round robin selection interleaves the outputs of thepair of VCO branch circuits.
 13. A transceiver as claimed in claim 8comprising at least three VCO branch circuits wherein round robinselection cascades the outputs of the at least three VCO branchcircuits.
 14. A transceiver as claimed in claim 10, wherein each VCObranch circuit further comprises a reset switch configured to inject areset signal into the corresponding injection locked system afteroscillation in the corresponding VCO branch circuit is turned off, toflush accumulated jitter in the injection locked system.
 15. A method ofoperating Voltage Controlled Oscillator (VCO) circuit, the methodcomprising: injecting a reference clock signal into a plurality of VCObranch circuits, each VCO branch circuit employing the reference clocksignal to provide a corresponding VCO output signal; and selecting theVCO output signal of each VCO branch circuit in a round robin fashion ofa period ΔT via a multiplexer and turning off a VCO in at least onedeselected VCO branch circuit, the multiplexer being configured tooutput the selected VCO output signal, wherein accumulated jitterincreases over time in each VCO branch circuit and jitter accumulationis limited below an acceptable threshold σ_(ΔT) via the round robinselection and turn off.
 16. A method as claimed in claim 15, whereineach VCO branch circuit comprises an injection locked system including acorresponding driver, the method comprising injecting the referenceclock signal into the corresponding injection locked system.
 17. Amethod as claimed in claim 16, wherein each injection locked systemcomprises a ring oscillator including a switch and a plurality ofinverters, the method further comprises actuating the switch to turn offthe corresponding VCO in a deselected VCO branch.
 18. A method asclaimed in claim 15 comprising a pair of VCO branch circuits whereinround robin selection interleaves the outputs of the pair of VCO branchcircuits.
 19. A method as claimed in claim 15 comprising at least threeVCO branch circuits wherein round robin selection cascades the outputsof the at least three VCO branch circuits.
 20. A method as claimed inclaim 16, wherein each VCO branch circuit further comprises a resetswitch, the method comprising injecting a reset signal into thecorresponding injection locked system after oscillation in thecorresponding VCO branch circuit is turned off to flush accumulatedjitter in the injection locked system.